LDMOS transistor structures are widely used in semiconductor devices for many types of transistor applications such as high voltage MOS field effect transistors. An LDMOS transistor comprises a lightly doped drain region to enhance the breakdown voltage. FIG. 1 shows a top view of a combined transistor structure including two MOSFET transistors. Both transistors are arranged within an active, for example, p doped area 1 that is isolated from the surroundings, by a so-called field region 11. The transistors share a common drain region consisting of a n+ doped region 9 surrounded by a n− doped region 8. Two source regions 6, 7 are arranged on the left and the right side of this drain region 8, 9. Thus, two channels are defined by the drain region 8, 9 and the two source regions 6 and 7, respectively. The broken lines indicate the gates 4 and 5 which are arranged above these channels. To the left and the right of the source regions 6 and 7, there are arranged p+ sinker structures 2 and 3 which extend from the surface of epitaxial layer to the bottom of the substrate to provide for a source connection on the backside of the substrate.
The active region 1 can be enclosed by a single step, the LOCal Oxidation of Silicon (LOCOS) as known in the art. This process creates a so called high stress field oxide bird's beak region which in combination with the p+ sinker structure implants 2 and 3 can result in a leakage path between the n+ drain and the p+ sinker structure along the interface stress and implant damage induced defect centers as indicated by arrows 10.
The conventional solution to prevent such a leakage is to increase the spacing between p+ and n+ implants to the bird's beak to suppress the leakage current. The disadvantages of such a measurement is, however, the increase of the non-functional part of the transistor fingers and the reduction of the isolation region.